{"id":20633,"date":"2023-03-01T05:19:20","date_gmt":"2023-03-01T05:19:20","guid":{"rendered":"http:\/\/care.ac.in\/engineering\/?p=20633"},"modified":"2023-03-06T05:28:04","modified_gmt":"2023-03-06T05:28:04","slug":"vlsi-soc-design-using-verilog-hdl","status":"publish","type":"post","link":"https:\/\/care.ac.in\/engineering\/2023\/03\/01\/vlsi-soc-design-using-verilog-hdl\/","title":{"rendered":"VLSI SoC Design using Verilog HDL"},"content":{"rendered":"<p>The Department of Electronics &amp; Communication Engineering, CARE college of engineering , Trichy organized a workshop on\u00a0<b>\u201cV<\/b><b>LSI SoC Design using Verilog HDL\u00a0<\/b><b>\u201d<\/b>, on 27.02.2023. The speaker of this event was Mr. P R Sivakumar \u2013 Founder &amp; CEO, Maven Silicon who has 20+ years of experience in Semiconductor Industry. It was attended by all the faculty members and students of ECE, Department.<br \/>\nDuring the session Mr. P R Sivakumar motivated and inspired the students towards the role and importance of VLSI design and application in Industry. He briefed about the Overview of VLSI Design, Chips and SoCs , SoC Design, RTL Design using Verilog HDL, Data Types, Data type concepts, Verilog Operators . Students\u00a0found the session useful.<\/p>\n<p><img fetchpriority=\"high\" decoding=\"async\" class=\" wp-image-20634 aligncenter\" src=\"https:\/\/care.ac.in\/engineering\/wp-content\/uploads\/sites\/7\/2023\/03\/UPDATED-INVITATION-WEBINAR-VLSI-1-200x300.jpg\" alt=\"\" width=\"435\" height=\"653\" \/><\/p>\n<p><img decoding=\"async\" class=\" wp-image-20635 aligncenter\" src=\"https:\/\/care.ac.in\/engineering\/wp-content\/uploads\/sites\/7\/2023\/03\/IMG_20230227_155255-300x138.jpg\" alt=\"\" width=\"809\" height=\"372\" \/><\/p>\n<p><img decoding=\"async\" class=\"alignnone wp-image-20637 aligncenter\" src=\"https:\/\/care.ac.in\/engineering\/wp-content\/uploads\/sites\/7\/2023\/03\/1-300x177.png\" alt=\"\" width=\"810\" height=\"478\" \/><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-20638 aligncenter\" src=\"https:\/\/care.ac.in\/engineering\/wp-content\/uploads\/sites\/7\/2023\/03\/2-300x186.png\" alt=\"\" width=\"808\" height=\"501\" \/><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-20639 aligncenter\" src=\"https:\/\/care.ac.in\/engineering\/wp-content\/uploads\/sites\/7\/2023\/03\/3-300x187.png\" alt=\"\" width=\"799\" height=\"498\" \/><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-20636 aligncenter\" src=\"https:\/\/care.ac.in\/engineering\/wp-content\/uploads\/sites\/7\/2023\/03\/5-300x223.png\" alt=\"\" width=\"794\" height=\"590\" \/><\/p>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>The Department of Electronics &amp; Communication Engineering, CARE college of engineering , Trichy organized a workshop on\u00a0\u201cVLSI SoC Design using Verilog HDL\u00a0\u201d, on 27.02.2023. The speaker of this event was Mr. P R Sivakumar \u2013 Founder &amp; CEO, Maven Silicon who has 20+ years of experience in Semiconductor Industry. It was attended by all the [&hellip;]<\/p>\n","protected":false},"author":8,"featured_media":20634,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[17,18],"tags":[],"post_folder":[],"class_list":["post-20633","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-ece-events","category-engineering-events"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v26.3 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>VLSI SoC Design using Verilog HDL - CARE College of Engineering<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/care.ac.in\/engineering\/2023\/03\/01\/vlsi-soc-design-using-verilog-hdl\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"VLSI SoC Design using Verilog HDL - CARE College of Engineering\" \/>\n<meta property=\"og:description\" content=\"The Department of Electronics &amp; Communication Engineering, CARE college of engineering , Trichy organized a workshop on\u00a0\u201cVLSI SoC Design using Verilog HDL\u00a0\u201d, on 27.02.2023. The speaker of this event was Mr. P R Sivakumar \u2013 Founder &amp; CEO, Maven Silicon who has 20+ years of experience in Semiconductor Industry. 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