VLSI SoC Design using Verilog HDL

The Department of Electronics & Communication Engineering, CARE college of engineering , Trichy organized a workshop on “VLSI SoC Design using Verilog HDL , on 27.02.2023. The speaker of this event was Mr. P R Sivakumar – Founder & CEO, Maven Silicon who has 20+ years of experience in Semiconductor Industry. It was attended by all the faculty members and students of ECE, Department.
During the session Mr. P R Sivakumar motivated and inspired the students towards the role and importance of VLSI design and application in Industry. He briefed about the Overview of VLSI Design, Chips and SoCs , SoC Design, RTL Design using Verilog HDL, Data Types, Data type concepts, Verilog Operators . Students found the session useful.

 

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